Fabrication method of multi-domain vertical alignment pixel structure

ABSTRACT

A fabrication method of a multi-domain vertical alignment pixel structure includes providing a substrate, forming a gate on the substrate, and forming an insulating layer on the substrate. A channel layer and a semiconductor layer are formed on the insulating layer. A source, a drain, and a capacitor-coupling electrode are formed. A passivation layer is formed to cover the source, the drain, a part of the channel layer, and a part of the semiconductor layer. A via hole is formed in the passivation layer to expose the drain, and a trench is formed in the passivation layer and the insulating layer. A lateral etched groove on the sidewall of the trench is formed to expose the side edge of the semiconductor layer. A first pixel electrode and a second pixel electrode are formed on the passivation layer at both sides of the trench, respectively.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of and claims the priority benefit of U.S. non-provisional application Ser. No. 11/693,732, filed on Mar. 30, 2007, now pending, which claims the priority benefit of Taiwan application serial no. 95136524, filed on Oct. 2, 2006. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a pixel structure and the fabrication method thereof, and more particular, to a multi-domain vertical alignment pixel structure (MVA pixel structure) and the fabrication method thereof.

2. Description of Related Art

The rapid development in the multimedia industry is largely attributed to the progress in the semiconductor devices and display apparatuses. In terms of displays, the liquid crystal displays (LCDs), with such advantages as high display quality, high space utilization, low power consumption and no radiation, have played a major role in the mainstream display market. In order to improve the LCD display quality, various LCDs with wide viewing angle have been developed and are available on the market today. The common LCDs with wide viewing angle are, for example, in-plane switching (IPS) LCDs, fringe field switching (FFS) LCDs and multi-domain vertical alignment (MVA) LCDs.

FIG. 1A is a diagram of a conventional multi-domain vertical alignment pixel structure. Referring to FIG. 1A, an MVA pixel structure 100 is disposed on a substrate 102. The MVA pixel structure 100 comprises an active device 110, a first pixel electrode 120, a second pixel electrode 122, a plurality of capacitor-coupling electrodes 130 and a common line 140. Specifically, the active device 110 is electrically connected to a scan line 104 and a data line 106. In addition, the active device 110 is electrically connected to the first pixel electrode 120 through a via hole C1. The scan line 104 delivers a scanning signal for turning on the active device 110, followed by delivering a display signal to the first pixel electrode 120 through the turned-on active device 110. On the other hand, the active device 110 is electrically connected to the capacitor-coupling electrode 130, while the common line 140 is electrically connected to a reference voltage.

As supposed to be, the first pixel electrode 120 is insulated from the second pixel electrode 122, and the second pixel electrode 122 is electrically coupled to the capacitor-coupling electrode 130 therebelow. In other words, once the active device 110 is turned on, the first pixel electrode 120 and the second pixel electrode 122 respectively take different voltages, so that the liquid crystal molecules (not shown) respectively corresponding to the first pixel electrode 120 and the second pixel electrode 122 have different orientations.

However, an ITO residue issue may occur during the process of the MVA pixel structure 100 so that the first pixel electrode 120 is electrically connected to the second pixel electrode 122. As shown by FIG. 1B, which is the sectional view along sectioning plane I-I′ in FIG. 1A, the residue R, remained during fabricating the first pixel electrode 120 and the second pixel electrode 122 and caused by the particles of environment or machine, may be located between the first pixel electrode 120 and the second pixel electrode 122. The residue R makes the first pixel electrode 120 and second pixel electrode 122 electrically connected to each other, which further leads to a poor display performance of the MVA pixel structure 100, and the problem needs to be solved properly.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to provide a fabrication method of an MVA pixel structure to effectively advance the production yield rate.

The present invention is directed to provide a MVA pixel structure having better reliability.

As embodied and broadly described herein, the present invention provides a MVA pixel structure, which includes an active device, a passivation layer, a first pixel electrode, a second pixel electrode, a capacitor-coupling electrode and a semiconductor layer. The active device is disposed on a substrate. The active device has an insulating layer extending to outside the active device and covering the substrate. The passivation layer covers the active device and a part of the insulating layer. The above-mentioned first pixel electrode and second pixel electrode are disposed on the passivation layer. The first pixel electrode is electrically connected to the active device, while the second pixel electrode is electrically insulated from the first pixel electrode. In addition, the capacitor-coupling electrode is disposed between the second pixel electrode and the substrate and is electrically connected to the active device. The above-mentioned semiconductor layer is disposed between the insulating layer and the passivation layer, wherein there is a trench in the insulating layer and the passivation layer, and a lateral etched groove is located on a sidewall of the trench. The lateral etched groove exposes the side edge of the semiconductor layer.

In an embodiment of the present invention, the above-mentioned lateral etched groove may be located on the sidewall of the trench adjacent to the first pixel electrode.

In an embodiment of the present invention, the above-mentioned lateral etched groove may be located on the sidewall of the trench adjacent to the first pixel electrode and on the sidewall of the trench adjacent to the second pixel electrode.

In an embodiment of the present invention, the above-mentioned lateral etched groove may be located on the sidewall of the trench adjacent to the second pixel electrode.

In an embodiment of the present invention, the above-mentioned semiconductor layer may include an amorphous silicon (a-Si) layer.

In an embodiment of the present invention, the above-mentioned MVA pixel structure further includes a storage capacitor disposed on the substrate and electrically connected to the active device.

In an embodiment of the present invention, the above-mentioned storage capacitor may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is disposed on the substrate, while the insulating layer covers the first capacitor electrode. The second capacitor electrode is disposed on the insulating layer over the first capacitor electrode and is electrically connected to the active device.

In an embodiment of the present invention, the above-mentioned capacitor-coupling electrode is electrically connected to the active device through the second capacitor electrode.

In an embodiment of the present invention, the above-mentioned capacitor-coupling electrode is located between the insulating layer and the passivation layer.

In an embodiment of the present invention, the above-mentioned active device includes a gate, a channel layer, a source and a drain. The gate is disposed on the substrate and the insulating layer covers the gate. The channel layer is disposed on the insulating layer over the gate. Additionally, the above-mentioned source and drain are disposed on the channel layer, while the source and the drain are located at both sides of the gate.

In an embodiment of the present invention, the above-mentioned active device further includes an ohmic contact layer disposed between the channel layer and the source and between the channel layer and the drain.

The present invention provides a fabrication method of an MVA pixel structure. The method includes the following steps. First, a substrate is provided and a gate is formed on the substrate. Next, an insulating layer is formed on the substrate to cover the gate. Then, a channel layer and a semiconductor layer are formed on the insulating layer, wherein the channel layer is located over the gate. After that, a source, a drain and a capacitor-coupling electrode are formed, wherein the source and drain are located on the channel layer and located at both sides of the gate, respectively. A passivation layer is formed to cover the source, the drain, a part of the channel layer and a part of semiconductor layer. A via hole is formed in the passivation layer to expose the drain and a trench is formed in the passivation layer and insulating layer such that a lateral etched groove is formed on the sidewall of the trench, wherein the lateral etched groove exposes the side edge of the semiconductor layer. A first pixel electrode and a second pixel electrode are formed on the passivation layer at both sides of the trench, respectively, wherein the first pixel electrode is electrically connected to the drain through the via hole, while the second pixel electrode is located over the capacitor-coupling electrode and is electrically insulated from the first pixel electrode.

In an embodiment of the present invention, the above-mentioned method for forming the trench may include using an etching process to remove a part of the passivation layer, a part of the semiconductor layer and a part of the insulating layer, wherein the etching process has an etching rate on the semiconductor layer higher than the etching rate on the passivation layer and the insulating layer.

In an embodiment of the present invention, the above-mentioned fabrication method of an MVA pixel structure further includes forming a storage capacitor on the substrate, wherein the storage capacitor is electrically connected to the drain.

In an embodiment of the present invention, the above-mentioned method for forming the storage capacitor includes the following steps. First, a first capacitor electrode is formed. Then, a second capacitor electrode is formed over the first capacitor electrode, wherein the drain is electrically connected to the second capacitor electrode.

In an embodiment of the present invention, the above-mentioned first capacitor electrode may be fabricated together with the gate, while the second capacitor electrode may be fabricated together with the source and the drain.

In an embodiment of the present invention, the above-mentioned capacitor-coupling electrode may be fabricated together with the source and the drain.

In an embodiment of the present invention, the above-mentioned fabrication method of an MVA pixel structure further includes forming an ohmic contact layer between the channel layer and the source and between the channel layer and the drain.

The present invention provides an MVA pixel structure, which includes an active device, a dielectric layer, a first pixel electrode, a second pixel electrode, a capacitor-coupling electrode and a lateral etched material layer. The active device and the dielectric layer are disposed on the substrate. The first pixel electrode and the second pixel electrode are disposed on the dielectric layer. The first pixel electrode is electrically connected to the active device, while the second pixel electrode is electrically insulated from the first pixel electrode. The above-mentioned capacitor-coupling electrode is disposed between the second pixel electrode and the substrate and is electrically connected to the active device. The above-mentioned lateral etched material layer is disposed in the dielectric layer, and the dielectric layer has a trench and a lateral etched groove located on the sidewall of the trench, wherein the lateral etched groove exposes the side edge of the lateral etched material layer.

The present invention provides a fabrication method of an MVA pixel structure, which includes the following steps. First, a substrate is provided. An active device, a dielectric layer, a capacitor-coupling electrode and a lateral etched material layer are formed on the substrate, wherein the capacitor-coupling electrode and the lateral etched material layer are located in the dielectric layer. A via hole, a trench and a lateral etched groove located on the sidewall of the trench are formed in the dielectric layer such that the lateral etched groove expose the side edge of the semiconductor layer. A first pixel electrode and a second pixel electrode are formed respectively on the dielectric layer at both sides of the trench, wherein the first pixel electrode is electrically connected to the active device through the via hole, while the second pixel electrode is electrically insulated from the first pixel electrode and located over the capacitor-coupling electrode.

Since the fabrication method of the MVA pixel structure in the present invention requires to form a lateral etched groove on the sidewall of the trench, the first pixel electrode and the second pixel electrode are assured to be electrically insulated from each other by the lateral etched groove, which contributes to effectively advance the production yield rate. Therefore, the MVA pixel structure fabricated by the fabrication method of the present invention demonstrates a much better performance.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1A is a diagram of a conventional multi-domain vertical alignment pixel structure.

FIG. 1B is the sectional view along sectioning plane I-I′ in FIG. 1A.

FIG. 2A-FIG. 2E are sectional views of the MVA pixel structure fabrication flow according to the first embodiment of the present invention.

FIG. 3A-FIG. 3D are schematic locally-enlarged top views of the MVA pixel structure fabrication flow according to the first embodiment of the present invention.

FIG. 4A-FIG. 4B are sectional views of the MVA pixel structure fabrication flow according to the second embodiment of the present invention.

FIG. 5A-FIG. 5B are sectional views of the MVA pixel structure fabrication flow according to the third embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS The First Embodiment

FIG. 2A-FIG. 2E are sectional views of the MVA pixel structure fabrication flow according to the first embodiment of the present invention and FIG. 3A-FIG. 3D are schematic locally-enlarged top views of the MVA pixel structure fabrication flow according to the first embodiment of the present invention. Referring to FIGS. 2A and 3A, first, a substrate 202 is provided and a gate 203 g is formed on the substrate 202. Generally, during forming the gate 203 g, a scan line 203 a, a first capacitor electrode 203 b and a common line 203 c may be formed simultaneously by the same photolithography and etching process for forming the gate 203 g, wherein the scan line 203 a is electrically connected to the gate 203 g, while the first capacitor electrode 203 b is electrically connected to the common line 203 c.

For example, a physical vapor deposition (PVD) process is used to deposit metal material entirely on the substrate 202 for fabricating the gate 203 g, the scan line 203 a, the first capacitor electrode 203 b and the common line 203 c. The metal material may be copper, aluminum, molybdenum, chrome, titanium, gold, aluminum alloy, molybdenum alloy, or other material with low resistivity. Next, the metal material is patterned by using a photolithography and etching process, so as to form the gate 203 g, the scan line 203 a, the first capacitor electrode 203 b and the common line 203 c simultaneously. After that, an insulating layer 204 is formed on the substrate 202 to cover the gate 203 g, the scan line 203 a, the first capacitor electrode 203 b and the common line 203 c. The material of the above-mentioned insulating layer 204 may be silicon oxide (SiOx), which is formed by a process using silicon nitride or TEOS (tetraethylorthosilicate, Si(OC₂H₅)₄) as the reaction gas source. For simplicity, the insulating layer 204 is omitted in FIG. 3A.

Referring to FIGS. 2B and 3B, a channel layer 205 c and a semiconductor layer 205 a are formed on the insulating layer 204, wherein the channel layer 205 c is located on the insulating layer 204 over the gate 203 g. Generally, the materials of the channel layer 205 c and the semiconductor layer 205 a may be amorphous silicon (a-Si), or other materials.

In order to reduce the contact impedance between the channel layer 205 c and a metal material, an ohmic contact layer 206 a is preferably formed on the surface of the channel layer 205 c. Specifically, an a-Si layer for example, is formed entirely on the insulating layer 204, then an N-type ion implanting process is performed to form a N-type doped a-Si layer located on the a-Si layer. After that, the a-Si layer and the N-type doped a-Si layer are patterned simultaneously by a photolithography and etching process such that the channel layer 205 c, the ohmic contact layer 206 a, the semiconductor layer 205 a and the N-type doped a-Si layer 206 b located on the semiconductor layer 205 a are formed simultaneously. It is noted that, the shapes and the positions of the semiconductor layer 205 a and the N-type doped a-Si layer 206 b shown in FIG. 2B and FIG. 3B is merely for illustration, the shapes and the positions are not limited and may be modified accordingly depending on the process requirement.

Referring to FIGS. 2C and 3C, a source 208 s, a drain 208 d, a capacitor-coupling electrode 208 a and a second capacitor electrode 208 b are formed, wherein the source 208 s and the drain 208 d are located on the channel layer 205 c and at both sides of the gate 203 g, respectively. As shown by FIG. 2C, the second capacitor electrode 208 b is formed on the insulating layer 204 over the first capacitor electrode 203 b so as to constitute a storage capacitor Cst together with the first capacitor electrode 203 b. It is seen from FIG. 3C, the capacitor-coupling electrode 208 a and the second capacitor electrode 208 b are electrically connected to each other and are fabricated by the same film, while the second capacitor electrode 208 b is electrically connected to the drain 208 d.

Generally, during forming the source 208 s, the drain 208 d, the capacitor-coupling electrode 208 a and the second capacitor electrode 208 b, a data lane 208 may be formed simultaneously, wherein the data line 208 and the source 208 c are electrically connected to each other and are fabricated by the same film. The above-mentioned gate 203 g, the channel layer 205 c, the ohmic contact layer 206 a, the source 208 s and the drain 208 d are together form an active device 210.

Specifically, a PVD process is used to deposit metal material entirely on the insulating layer 204 for fabricating the data line 208, the source 208 s, the drain 208 d, the capacitor-coupling electrode 208 a and the second capacitor electrode 208 b. After that, a photolithography and etching process is performed to pattern the metal material so as to form the source 208 s, the drain 208 d, the data line 208, the capacitor-coupling electrode 208 a and the second capacitor electrode 208 b simultaneously. During forming the source 208 s and the drain 208 d, a part of the ohmic contact layer 206 a, a part of the channel layer 205 c and the N-type doped a-Si layer 206 b (as shown in FIG. 2B) on the semiconductor layer 205 a are removed together. Referring to FIG. 2C, a passivation layer 220 is formed on the substrate 202 to cover the source 208 s, the drain 208 d, a part of the channel layer 205 c and a part of the semiconductor layer 205 a. Generally, the material of the passivation layer 220 may be silicon oxide, silicon nitride, silicon oxynitride or polyimide.

Referring to FIG. 2D, a via hole C2 is formed in the passivation layer 220 to expose the second capacitor electrode 208 b connected with the drain 208 d, and a trench T2 and a lateral etched groove S are formed in the passivation layer 220 and the insulating layer 204, wherein the lateral etched groove S is located on the sidewall of the trench T2. Specifically, the lateral etched groove S exposes the side edge of the semiconductor layer 205 a. The method for forming the above-mentioned trench T2 and lateral etched groove S is an etching process for removing a part of passivation layer 220, a part of semiconductor layer 205 a and a part of insulating layer 204, for example. It is noted that, the etching process has an etching rate on the semiconductor layer 205 a higher than the etching rate on the passivation layer 220 and the insulating layer 204. In this way, the semiconductor layer 205 a is removed more effectively so as to form the lateral etched groove S.

Referring to FIGS. 2E and 3D, a first pixel electrode 230 a and a second pixel electrode 230 b are formed on the passivation layer 220 at both sides of the trench T2, respectively, wherein the first pixel electrode 230 a is electrically connected to the drain 208 d through the via hole C2 and the second capacitor electrode 208 b, while the second pixel electrode 230 b is located over the capacitor-coupling electrode 208 a. It is noted that, the second pixel electrode 230 b is electrically insulated from the first pixel electrode 230 a.

Since a lateral etched groove S is formed on the sidewall of the trench T2, even though the material for forming the first pixel electrode 230 a and the second pixel electrode 230 b has a residue remained on the sidewall and the bottom of the trench T2 (as shown by FIG. 2E), the first pixel electrode 230 a and the second pixel electrode 230 b are still assured to be electrically insulated from each other. Therefore, the fabrication method of an MVA pixel structure provided by the present invention can effectively advance the production yield rate.

The MVA pixel structure 200 fabricated by the above-mentioned method is shown in FIGS. 2E and 3D. The MVA pixel structure 200 of the present invention comprises an active device 210, a passivation layer 220, a first pixel electrode 230 a, a second pixel electrode 230 b, a semiconductor layer 205 a and a capacitor-coupling electrode 208 a, wherein the active device 210 is disposed on the substrate 202 and electrically connected to the scan line 203 a and the data line 208. Anyone skilled in the art knows that the layout of the active device 210 in FIG. 3D may be modified according to different design requirement.

Specifically, the active device 210 may be a thin film transistor with a bottom gate, as shown in FIG. 2E, an insulating layer 204 is extended to outside the active device 210 and covers the substrate 202, while the passivation layer 220 covers the active device 210 and a part of the insulating layer 204. The active device 210 of the embodiment may further include an ohmic contact layer 206 a (as shown in FIG. 2E) disposed between the channel layer 205 c and the source 208 s and between the channel layer 205 c and the drain 208 d.

In addition, the first pixel electrode 230 a and the second pixel electrode 230 b are disposed on the passivation layer 220, wherein the first pixel electrode 230 a is electrically connected to the active device 210 through the via hole C2, while the second pixel electrode 230 b is electrically insulated from the first pixel electrode 230 a. The scan line 203 a delivers a scanning signal for turning on the active device 210, followed by delivering a display signal to the first pixel electrode 230 a through the data line 208 and the turned-on active device 210. Besides, the capacitor-coupling electrode 208 a is disposed between the second pixel electrode 230 b and the substrate 202 and the capacitor-coupling electrode 208 a is electrically connected to the active device 210.

As shown by FIG. 2E, the above-mentioned semiconductor layer 205 a is disposed between the insulating layer 204 and the passivation layer 220, wherein the insulating layer 204 and the passivation layer 220 have a trench T2 and a lateral etched groove S located on the sidewall of the trench T2, and the lateral etched groove S exposes the side edge of the semiconductor layer 205 a. It is noted that, the semiconductor layer 205 a located in the lateral etched groove S may be other kind of materials. For example, when the semiconductor layer 205 a (i.e. the lateral etched material layer), the insulating layer 204 and the passivation layer 220 are removed by the same etchant, the lateral etched material layer having an etching rate higher than the etching rate of the insulating layer 204 and the passivation layer 220 is required. Therefore, the material of the lateral etched material layer is not limited to semiconductor.

The MVA pixel structure 200 of the present invention may further include a storage capacitor Cst disposed on the substrate 202. Specifically, the storage capacitor Cst may include a first capacitor electrode 203 b and a second capacitor electrode 208 b, wherein the first capacitor electrode 203 b is disposed on the substrate 202, while the second capacitor electrode 208 b is disposed on the insulating layer 204 over the first capacitor electrode 203 b. In addition, the storage capacitor Cst is electrically connected to the active device 210 through the second capacitor electrode 208 b. On the other hand, the capacitor-coupling electrode 208 a located between the insulating layer 204 and the passivation layer 220 is electrically connected to the active device 210 through the second capacitor electrode 208 b.

The Second Embodiment

The second embodiment is similar to the first embodiment except that the present embodiment adjusts the relative position between the trench T2 and semiconductor layer 205 a so as to form the lateral etched groove S on the sidewall of the trench T2 only adjacent to the first pixel electrode 230 a, as shown in FIG. 4A and FIG. 4B.

Referring to FIG. 4B, a first pixel electrode 230 a and a second pixel electrode 230 b are formed on the passivation layer 220 at both sides of the trench T2, respectively. The first pixel electrode 230 a and the second pixel electrode 230 b in the MVA pixel structure 300 of the embodiment are also assured to be electrically insulated from each other by the lateral etched groove S. In other words, even though the material for forming the first pixel electrode 230 a and the second pixel electrode 230 b has a residue remained on the sidewall and the bottom of the trench T2 (as shown by FIG. 4B), the first pixel electrode 230 a and the second pixel electrode 230 b are still assured to be electrically insulated from each other by the lateral etched groove S.

The Third Embodiment

The third embodiment is similar to the first embodiment except that the present embodiment adjusts the relative position between the trench T2 and semiconductor layer 205 a so as to form the lateral etched groove S on the sidewall of the trench T2 only adjacent to the second pixel electrode 230 b, as shown in FIG. 5A and FIG. 5B.

Referring to FIG. 5B, a first pixel electrode 230 a and a second pixel electrode 230 b are formed on the passivation layer 220 at both sides of the trench T2, respectively. The first pixel electrode 230 a and the second pixel electrode 230 b in the MVA pixel structure 400 of the embodiment are also assured to be electrically insulated from each other by the lateral etched groove S.

In summary, since a lateral etched groove is formed on the sidewall of the trench, the first pixel electrode and the second pixel electrode are assured to be electrically insulated from each other by the lateral etched groove during fabricating the first pixel electrode and the second pixel electrode, which contributes to effectively advance the production yield rate. Therefore, the MVA pixel structure by using the fabrication method of the present invention has good reliability.

The above description provides a full and complete description of the embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims. 

1. A fabrication method of a multi-domain vertical alignment pixel structure, comprising: providing a substrate; forming a gate on the substrate; forming an insulating layer on the substrate to cover the gate; forming a channel layer and a semiconductor layer on the insulating layer, wherein the channel layer is located over the gate; forming a source, a drain and a capacitor-coupling electrode, wherein the source and the drain are located on the channel layer and at both sides of the gate, respectively; forming a passivation layer to cover the source, the drain, a part of the channel layer and a part of the semiconductor layer; forming a via hole in the passivation layer to expose the drain, and forming a trench in the passivation layer and the insulating layer and forming a lateral etched groove located on the sidewall of the trench to expose the side edge of the semiconductor layer; and forming a first pixel electrode and a second pixel electrode on the passivation layer at both sides of the trench, respectively, wherein the first pixel electrode is electrically connected to the drain through the via hole, while the second pixel electrode is located over the capacitor-coupling electrode and electrically insulated from the first pixel electrode.
 2. The fabrication method according to claim 1, wherein a method for forming the trench comprises using an etchant to remove a part of the passivation layer, a part of the semiconductor layer and a part of the insulating layer, wherein the etchant has an etching rate on the semiconductor layer higher than an etching rate on the passivation layer and on the insulating layer.
 3. The fabrication method according to claim 1, further comprising forming a storage capacitor on the substrate, wherein the storage capacitor is electrically connected to the drain.
 4. The fabrication method according to claim 1, wherein a method for forming the storage capacitor comprises: forming a first capacitor electrode; and forming a second capacitor electrode over the first capacitor electrode, wherein the second capacitor electrode is electrically connected to the drain.
 5. The fabrication method according to claim 4, wherein the first capacitor electrode and the gate are formed simultaneously, while the second capacitor electrode and the source and the drain are formed simultaneously.
 6. The fabrication method according to claim 1, wherein the capacitor-coupling electrode and the source and the drain are formed simultaneously.
 7. The fabrication method according to claim 1, further comprising forming an ohmic contact layer between the channel layer and the source/drain.
 8. A fabrication method of a multi-domain vertical alignment pixel structure, comprising: providing a substrate; forming a gate on the substrate; forming an active device, a dielectric layer, a capacitor-coupling electrode and a lateral etched material layer on the substrate, wherein the capacitor-coupling electrode and the lateral etched material layer are located in the dielectric layer; forming a via hole and a trench in the dielectric layer and forming a lateral etched groove on the sidewall of the trench to expose the side edge of the semiconductor layer; and forming a first pixel electrode and a second pixel electrode on the dielectric layer at both sides of the trench, respectively, wherein the first pixel electrode is electrically connected to the active device through the via hole, while the second pixel electrode is electrically insulated from the first pixel electrode and located over the capacitor-coupling electrode. 